The present invention relates to semiconductor processing and, more particularly, to fabrication of a metal interconnect structure for an integrated circuit. A major objective of the present invention is to minimize voids between a spin-on glass and an underlying silicon dioxide layer.
Much of modern technological progress is identified with miniaturization of integrated circuits. Miniaturization allows for increased functionality by increasing the number of circuits that can be integrated onto a single device. Increased processing speeds are also achieved as the capacitances and distances between circuit elements are reduced. In addition, miniaturization can lower costs by increasing the number of integrated circuit devices that can be made together.
Patterned metal interconnect layers are generally used to provide the "integration" of integrated circuits. Two or more metal layers are usually required to provide for non-shorting cross over of electrical connections. The metal layers are electrically isolated from each other by an intermetal dielectric; where intermetal connections are required, metal vias extend through the intermetal dielectric. The metal interconnect structure is, in turn, electrically isolated from the circuit elements below by a submetal dielectric; contact vias through the submetal dielectric provide access to the integrated circuit elements.
One of the challenges in building an integrated circuit up layer-by-layer is that significant nonplanarities arise. For example, after the first metal is patterned, the locations from which metal has been removed are lower than adjacent locations where metal remains. If these nonpanarities are carried through formation of the intermetal dielectric, problems can arise when the second metal is deposited. For example, the second metal can have difficulty conforming to the nonplanar contours; this can lead to electrical discontinuities, lower performance and shorter device lifetimes.
To improve the planarity for the second metal, a spin-on glass can be used in the intermetal dielectric. A spin-on glass is applied as a liquid, which fills in the troughs, while maintaining a relatively planar upper surface. The liquid is viscous, so there is some conformity to large scale nonplanarities. The spin-on glass is polymerized. Further planarization can be achieved by polishing and/or etchback.
One problem with spin-on glass is that it contains moisture and other solvents that can attack adjacent metal layers. This problem can be addressed by sandwiching the spin-on glass between deposited silicon dioxide layers.
While it provides a planar surface for overlaying layers, the spin-on glass itself is deposited on a non-planar surface. The spin-on glass may fail to conform to the underlying nonplanarities, leaving voids at the interface with the lower silicon dioxide layer. These voids can impair the dielectric character of the intermetal dielectric. In addition, the voids can serve as sites for moisture to accumulate and attack adjacent features, such as metal vias. Furthermore, the voids can serve as channels through which wet etches can reach unintended areas, impairing or destroying the integrated circuit.
What is needed is a method of applying spin-on glass that results in improved conformity to an underlying nonplanar silicon dioxide layer so that voids are minimized. Preferably, the method would minimally impact process complexity, integrated circuit handling, and fabrication throughput.